The present disclosure relates to a DA (Digital-Analog) converter, a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus, and in particular, to a DA converter, a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic apparatus capable of reducing a settling time and accelerating the switching speed of gain settings.
A known solid-state imaging device has an AD (Analog-Digital) converter to perform AD conversion of the pixel signal of each pixel. The AD converter compares an analog pixel signal output from each pixel with a reference signal having a ramp waveform (hereinafter also referred to as a ramp signal) whose level (voltage) changes stepwise with time. In parallel with the comparison processing, the AD converter also performs count processing to determine the digital value of the pixel signal based on a count value at a time at which the comparison processing is finished (see, for example, Japanese Patent Application Laid-open No. 2007-59991).
Accordingly, the solid-state imaging device also has a DA converter to generate the ramp signal and supply the same to the AD converter.
FIGS. 1A and 1B are schematic configuration diagrams of current-control-type DA converters used to generate a ramp signal.
FIG. 1A shows the configuration of a DA converter 1a based on a ground GND, and FIG. 1B shows the configuration of a DA converter 1b based on a power supply voltage VDD.
Each of the DA converters 1a and 1b includes a current source I1 composed of a plurality of basic current source cells that generate a constant current, a reference resistor R1 serving as a current-voltage conversion section, and a counter CNT1.
In the ground-based DA converter 1a, the reference resistor R1 is connected to the ground GND. In the power-supply-voltage-based DA converter 1b, the reference resistor R1 is connected to the power supply voltage VDD.
Each of the DA converters 1a and 1b counts a clock CLK input to the counter CNT1, determines the number of the basic current source cells selected by the current source I1 based on the count value, and supplies the current to the reference resistor R1 to set the voltage of a resistor value as a reference voltage serving as a ramp signal.
FIG. 2 is a circuit diagram showing a specific configuration example of the ground-based DA converter 1a shown in FIG. 1A.
The DA converter 1a in FIG. 2 has a ramp signal generation part 2, a gain control signal generation part 3, a counter decoder 4, and a gain decoder 5.
The ramp signal generation part 2 includes a current source transistor group 21, a cascade transistor group 22, a counter selection switch group 23, and a reference resistor R2 serving as a current-voltage conversion section.
The gain control signal generation part 3 includes transistors Tr1 to Tr8 and a capacitor CP1. Here, the transistor Tr2 includes a plurality of transistors and is capable of changing its entire transistor size by selecting a predetermined number of transistors. In this sense, the transistor Tr2 will be referred to as a variable transistor Tr2 below.
The transistor Tr1, the plurality of transistors constituting the variable transistor Tr2, and the transistors Tr5 and Tr6 are made of n channel transistors (NMOS transistors), and the transistors Tr3, Tr4, Tr7, and Tr8 are made of p channel transistors (PMOS transistors).
The ramp signal generation part 2 generates a ramp signal corresponding to a count value DI1, i.e., the decoding result of the counter decoder 4. At this time, the gain of the generated ramp signal (the inclination of the ramp signal) is adjusted according to a bias voltage Vb supplied as a gain control signal from the gain control signal generation part 3.
The current source transistor group 21 includes m (m>1) current source transistors DTr-1 to DTr-m, the cascade transistor group 22 includes m cascade transistors CTr-1 to CTr-m, and the counter selection switch group 23 includes m selection switches CSW-1 to CSW-m.
One of the current source transistors DTr of the current source transistor group 21 is connected in series to one of the cascade transistors CTr of the cascade transistor group 22 and one of the selection switches CSW of the counter selection switch group 23. The current source transistors DTr and the cascade transistors CTr are made of p channel transistors (PMOS transistors).
The gate of the current source transistor DTr-1 is connected to the gate and the drain of the transistor Tr3 of the gain control signal generation part 3, and the current source transistor DTr-1 and the transistor Tr3 constitute a current mirror circuit. The source of the current source transistor DTr-1 is connected to the power supply voltage VDD. The drain of the current source transistor DTr-1 is connected to the source of the cascade transistor CTr-1, and the drain of the cascade transistor CTr-1 is connected to the selection switch CSW-1.
In addition, the gate of the cascade transistor CTr-1 is connected to the gate and the drain of the transistor Tr7 of the gain control signal generation part 3. As will be described later, the source of the transistor Tr7 is connected to the drain and the gate of the transistor Tr8 of the gain control signal generation part 3 and the source of the transistor Tr8 is connected to the power supply voltage VDD. Accordingly, the current source transistor DTr-1, the cascade transistor CTr-1, and the transistors Tr3 and Tr7 of the gain control signal generation part 3 constitute a cascade current mirror circuit. The cascade transistor CTr-1 reduces fluctuations in the voltage between the source and the drain of the current source transistor DTr-1 to stabilize the bias point of the current source transistor DTr-1 (improve the integral non-linearity (INL) of the DA converter 1a).
The drain of the cascade transistor CTr-1 is connected to an output node ND1 of the DA converter 1a via the selection switch CSW-1. In addition, the reference resistor R2 serving as the current-voltage conversion section is arranged between the output node ND1 and the ground GND.
Similarly, the other current source transistors DTr-2 to DTr-m of the current source transistor group 21 and the cascade transistors CTr-2 to CTr-m of the cascade transistor group 22 also constitute a cascade current mirror circuit with the transistors Tr3 and Tr7 of the gain control signal generation part 3.
The gain control signal generation part 3 generates the bias voltage Vb as the gain control signal corresponding to the gain setting value DGI1, i.e., the decoding result of the gain decoder 5. The gain control signal generation part 3 outputs the generated bias voltage Vb to the ramp signal generation part 2 as a gain adjusting signal.
In addition, the gain control signal generation part 3 generates a bias voltage Vcas (hereinafter also referred to as a cascade control voltage Vcas) supplied to the cascade transistors CTr of the cascade transistor group 22 and outputs the same to the ramp signal generation part 2.
The gain control signal generation part 3 has the diode-connected transistor Tr1 and the variable transistor Tr2 whose transistor size changes according to the gain setting value DGI1, i.e., the decoding result of the gain decoder 5. A reference current Ib is supplied to the drain and the gate of the transistor Tr1, and the source of the transistor Tr1 is connected to the ground GND.
The variable transistor Tr2 includes the plurality of transistors, and each of the gates of the transistors is connected to the gate of the transistor Tr1 to constitute a current mirror circuit. The variable transistor Tr2 changes a gain control current Igain flowing through the variable transistor Tr2 by selecting a predetermined number of transistors according to the decoding value DGI1 of a digital gain setting signal. The capacitor CP1 is connected to a connection node ND2 between the transistor Tr1 and the variable transistor Tr2.
The sources of the transistors Tr3 and Tr4 are connected to the power supply voltage VDD. The gate and the drain of the transistor Tr3 are connected to the gate of the transistor Tr4, the drain of the variable transistor Tr2, and the gates of the respective current source transistors DTr of the ramp signal generation part 2. The transistors Tr3 and Tr4 constitute a current mirror circuit.
The drain of the transistor Tr4 is connected to the drain and the gate of the transistor Tr5 and the gate of the transistor Tr6. The sources of the transistors Tr5 and Tr6 are connected to the ground GND, and the drain of the transistor Tr6 is connected to the drain of the transistor Tr7. The transistors Tr5 and Tr6 also constitute a current mirror circuit.
The source of the transistor Tr8 is connected to the power supply voltage VDD, and the gate and the drain of the transistor Tr8 are connected to the source of the transistor Tr7. The gate and the drain of the transistor Tr7 are connected to the source of the transistor Tr6 and the gates of the respective cascade transistors CTr of the ramp signal generation part 2.
The counter decoder 4 decodes an input digital input signal and controls the ON/OFF of the selection switches CSW-1 to CSW-m of the counter selection switch group 23 according to the resulting count value D11.
The gain decoder 5 decodes an input digital gain setting signal and changes (controls) the transistor size of the variable transistor Tr2 according to the resulting gain value DGI1.
Next, a description will be given of the operations of the DA converter 1a in FIG. 2.
A predetermined number of transistors are selected from the variable transistor Tr2 according to the gain setting value DGI1, i.e., the decoding result of the gain decoder 5. Based on the reference current Ib flowing through the transistor Tr1, a current flows through the selected one or more transistors of the variable transistor Tr2. By the addition of these currents, the gain control current Igain is generated. Then, the gain control signal of the bias voltage Vb corresponding to the gain control current Igain flowing through the variable transistor Tr2 is supplied to the gates of the respective current source transistors DTr of the current source transistor group 21.
In addition, a current mirroring the gain control current Igain is supplied from the transistor Tr4 to the transistor Tr5, and the transistors Tr5 and Tr6 constituting the current mirror circuit generate a cascade transistor control current Icas. Thus, the control signal of the cascade control voltage Vcas is supplied to the gates of the respective cascade transistors CTr of the cascade transistor group 22.
Moreover, at least one of the m selection switches CSW-1 to CSW-m is turned on (selected) according to the count value DI1, i.e., the decoding result of the counter decoder 4. Next, an output current corresponding to the gain control signal of the bias voltage Vb flows through the current source transistors DTr and the cascade transistors CTr connected in series to the selected selection switches CSW. Then, the output currents flowing through the one or more selection switches CSW are added together at an output node ND1 and turn into a ramp output current Iramp. The ramp output current Iramp is converted into a voltage signal by the reference resistor R2 serving as the current-voltage conversion section and output as the ramp signal.
As described above, in the DA converter 1a, the gain control current Igain changes according to the decoding result DGI1 of the digital gain setting signal, i.e., the gain setting value. Further, with a change in the gain control current Igain, the bias voltage Vb supplied to the current source transistors DTr and the cascade control voltage Vcas supplied to the cascade transistors CTr also change. Accordingly, at the switching of gain settings, a settling time for stabilizing the current and the voltage arises.